## EGR 270 - Fundamentals of Computer Engineering at Virginia Western Community College

### Course Description

Effective: 2015-05-01

Covers the design and organization of digital systems, including number systems, Boolean algebra, logic gates, Karnaugh maps, combinational and sequential logic circuits, timing diagrams, and synchronous and asynchronous controllers. Introduces hardware description language (HDL) and assembly language programming.
Lecture 3 hours. Laboratory 2 hours. Total 5 hours per week.
4 credits

### General Course Purpose

This course covers the design and organization of digital systems, including number systems, Boolean algebra, logic gates, Karnaugh maps, combinational and sequential logic circuits, timing diagrams, and synchronous and asynchronous controllers. It also introduces Engineering majors to hardware description language (HDL) and assembly language programming.

### Course Objectives

• Represent numbers and perform arithmetic operations in various bases and convert between bases.
• Express, simplify, and minimize Boolean functions through various methods, including truth tables, Boolean algebra and Karnaugh maps.
• Implement logical expressions using defined logic functions.
• Analyze and synthesize combinational logic circuits.
• Analyze and synthesize sequential logic circuits, including the use of state diagrams, state tables, excitation tables and state equations.
• Implement logic circuits using Hardware Description Language (HDL) and Field Programmable Gate Arrays (FPGAs).
• Identify concepts in computer organization.
• Simulate logic circuits and explore concepts in computer organization through the use of HDL and assembly language.

### Major Topics to be Included

• Digital Computers and Information
• Digital systems
• Number systems
• Decimal and alphanumeric codes
• Combinational Logic Circuits
• Logic Expressions and Simplification
• Boolean algebra
• Logic gates & implementing logic expressions
• Truth tables
• Canonical forms and standard forms
• Implicants, essential and prime
• Reduction by Karnaugh maps (2-5 variable)
• Product of Sums (POS) and Sum of Products (SOP) implementations
• Don't care conditions
• Multiple-level circuit implementation
• Combinational Logic Design
• Design procedure
• Hierarchical design
• Verification
• Technology mapping (Ex: NAND and NOR implementations)
• Rudimentary Logic Functions
• Decoders and enabling
• Encoders, priority encoders, and multiplexers
• Implementing combinational logic functions using decoders and multiplexers
• Hardware Description Language (HDL) for combinational logic circuits
• Arithmetic Functions and Circuits
• Binary addition, subtraction, and multiplication
• Other arithmetic functions
• Sequential Circuits
• Flip-flops and latches
• Sequential circuit analysis
• Mealy models and Moore models
• State diagrams and state tables
• Sequential circuit timing
• Design of sequential circuits
• Hardware Description Language (HDL) for sequential circuits
• Selected Design Topics A. The Design Space B. Gate propagation delay C. Flip-flop timing and sequential circuit timing D. ROM, Programmable Logic Devices (PLDs), and Field Programmable Gate Arrays (FPGAs)
• Registers and Counters A. Registers and register operations B. Synchronous and ripple counters C. Asynchronous counters versus synchronous counters
• Assembly Language
• Assembly language and computer architecture
• Instruction sets and addressing modes
• 68HC11 Microcontroller
• Programming concepts
• Memory
• Tri-state devices
• Random Access Memory (RAM)
• Lab Topics
• Lab #1 Introduction to Logic
• Lab #2 Characteristics of TTL gates
• Lab #3 Combinational Logic Circuits
• Lab #4 7-segment displays, decoders and multiplexers
• Lab #5 VHDL Combinational Logic Circuit
• Lab #6 Sequential Counters
• Lab #7 VHDL Sequential Logic Circuit
• Lab #8 Assembly Language/MicroStamp 11

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